#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/sromc.h>
#include <netdev.h>
#include <asm/mach-types.h>
#include <spl.h>
#include <debug_uart.h>
#include <asm/arch/cpu.h>
#include <asm/arch/uart.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>

#ifdef CONFIG_DRIVER_DM9000
#include <net.h>
#include <netdev.h>
#endif

#ifdef CONFIG_SPL_BUILD

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_DRIVER_DM9000

static void dm9000_srom_init(unsigned int bank)
{
    unsigned long bc = SMC_BC_TACS(0) | SMC_BC_TCOS(0) | SMC_BC_TACC(5) | SMC_BC_TCOH(0) | SMC_BC_TAH(0) | SMC_BC_TACP(0);
    unsigned long bw = SMC_DATA16_WIDTH(bank) | SMC_BYTE_ENABLE(bank);

    s5p_config_sromc(bank, bw, bc);
}

static void dm9000_pre_init(unsigned int bank)
{
    unsigned int val = 0;
    struct gpio_info *gpio = get_gpio_data();
    struct s5p_gpio_bank *mp0_1con = (struct s5p_gpio_bank *)(gpio->reg_addr + (S5PC110_GPIO_MP010 << 2));
 
    val = readl(mp0_1con);
    val &= ~(0xf << (bank * 4));
    val |= (0x2 << (bank * 4));

    val &= ~(0xff << 24);
    val |= 0x22 << 24;

    writel(val, mp0_1con);

    dm9000_srom_init(bank);

}

#endif

void board_boot_order(u32 *spl_boot_list)
{
#ifdef CONFIG_SPL_NAND_SUPPORT
    spl_boot_list[0] = BOOT_DEVICE_NAND;
#endif
}

void spl_board_init(void)
{
#ifdef CONFIG_DRIVER_DM9000
    dm9000_initialize(NULL);
#endif
}

void board_init_f(ulong dummy)
{
    arch_cpu_init();
    gd->flags |= GD_FLG_SPL_INIT;
    preloader_console_init();
#ifdef CONFIG_DRIVER_DM9000
    struct s5pc110_clock *base =(struct s5pc110_clock *)samsung_get_base_clock();
    unsigned long clk_gate = readl(&base->gate_ip1);
    clk_gate |= 1 << 26;        /* Enable SROM CLK */
    writel(clk_gate, &base->gate_ip1);
    dm9000_pre_init(CONFIG_SPL_DM9000_SROM_BANK);
#endif
}

void spl_display_print()
{
    printf("BOARD:mini210\nSoC:%s rev:%d\nRAM:%uMB\nCLOCK:%luMHz\n", 
    cpu_is_s5pc110() ? "S5PV210" : "S5PC110",s5p_get_cpu_rev(), 
    PHYS_SDRAM_0_SIZE / 1024 / 1024, 
    get_arm_clk() / 1000 / 1000
    );
}

void spl_perform_fixups(struct spl_image_info *spl_image)
{

}

#endif
